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CS4382A
114 dB, 192 kHz 8-Channel D/A Converter
Features
! Advanced Multi-bit Delta Sigma Architecture ! 24-bit Conversion ! Up to 192 kHz Sample Rates ! 114 dB Dynamic Range ! -100 dB THD+N ! Direct Stream Digital Mode ! On-Chip 50 kHz Filter ! Matched PCM and DSD Analog Output Levels ! Selectable Digital Filters ! Volume Control with 1-dB Step Size and Soft
Description
The CS4382A is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, one-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator whitch includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low-pass filter with differential analog outputs. The CS4382A also has a proprietary DSD processor which allows for 50 kHz on-chip filtering without an intermediate decimation stage. The CS4382A is available in a 48-pin LQFP package in both Commercial (-10 to +70C) and Automotive grades (-40 to +85C). The CDB4382A Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 47 for complete details. The CS4382A accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These features are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV's, mixing consoles, effects processors, sound cards and automotive audio systems.
Ramp
! Low Clock-Jitter Sensitivity ! +5 V Analog Supply, +2.5 V Digital Supply ! Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Control & Serial Audio Port Supplies = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Level Translator
Hardware Mode or I2C/SPI Software Mode Control Data
Register/Hardware Configuration
Internal Voltage Reference
Reset
PCM Serial Audio Input Level Translator Serial Interface
8
Volume Controls
Digital Filters
Multi-bit Modulators
Switch-Cap DAC and Analog Filters
8 8
Differential Outputs
DSD Audio Input
DSD Processor -50 kHz filter
External Mute Control
2
Mute Signals
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
NOVEMBER '05 DS618PP2
CS4382A
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 3. TYPICAL CONNECTION DIAGRAM .............................................................................. 18 4. APPLICATIONS ................................................................................................................................... 20 4.1 Master Clock ................................................................................................................................... 20 4.2 Mode Select .................................................................................................................................... 20 4.3 Digital Interface Formats ................................................................................................................ 22 4.4 Oversampling Modes ...................................................................................................................... 23 4.5 Interpolation Filter ........................................................................................................................... 23 4.6 De-Emphasis .................................................................................................................................. 23 4.7 ATAPI Specification ........................................................................................................................ 24 4.8 Direct Stream Digital (DSD) Mode .................................................................................................. 25 4.9 Grounding and Power Supply Arrangements ................................................................................. 25 4.9.1 Capacitor Placement ............................................................................................................. 25 4.10 Analog Output and Filtering .......................................................................................................... 25 4.11 Mute Control ................................................................................................................................. 26 4.12 Recommended Power-Up Sequence ........................................................................................... 27 4.12.1 Hardware Mode ................................................................................................................... 27 4.12.2 Software Mode .................................................................................................................... 27 4.13 Recommended Procedure for Switching Operational Modes ....................................................... 27 4.14 Control Port Interface ................................................................................................................... 27 4.14.1 MAP Auto Increment ........................................................................................................... 28 4.14.2 IC Mode .............................................................................................................................. 28 4.14.2.1 IC Write ................................................................................................................... 28 4.14.2.2 IC Read .................................................................................................................. 28 4.14.3 SPITM Mode ......................................................................................................................... 29 4.14.3.1 SPI Write .................................................................................................................. 29 4.15 Memory Address Pointer (MAP) ............................................................................................. 30 4.16 INCR (Auto Map Increment Enable) ............................................................................................. 30 4.16.1 MAP4-0 (Memory Address Pointer) .................................................................................... 30 5. REGISTER QUICK REFERENCE ........................................................................................................ 31 6. REGISTER DESCRIPTION .................................................................................................................. 32 6.1 Mode Control 1 (address 01h) ........................................................................................................ 32 6.1.1 Control Port Enable (CPEN) .................................................................................................. 32 6.1.2 Freeze Controls (Freeze) ...................................................................................................... 32 6.1.3 Master Clock DIVIDE ENABLE (mclkdiv) .............................................................................. 32 6.1.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 32 6.1.5 Power Down (PDN) ............................................................................................................... 33 6.2 Mode Control 2 (address 02h) ....................................................................................................... 33 6.2.1 Digital Interface Format (dif) .................................................................................................. 33 6.2.2 Mode Control 3 (address 03h) .............................................................................................. 34 6.2.3 Soft Ramp and Zero Cross CONTROL (SZC) ...................................................................... 34 6.2.4 Single Volume Control (Snglvol) ........................................................................................... 34 6.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ....................................................................... 35 6.2.6 MUTEC Polarity (MUTEC+/-) ................................................................................................ 35 6.2.7 Auto-Mute (AMUTE) ............................................................................................................. 35 6.3 Mutec Pin Control (MUTEC) ........................................................................................................... 35 6.4 Filter Control (address 04h) ........................................................................................................... 36 6.4.1 Interpolation Filter Select (FILT_SEL) ................................................................................... 36 6.4.2 De-Emphasis Control (DEM) ................................................................................................. 36 6.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ..................................................... 36 6.5 Invert Control (address 05h) .......................................................................................................... 37 2 DS618PP2
CS4382A
6.5.1 Invert Signal Polarity (Inv_Xx) ............................................................................................... 37 6.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h) Mixing Control Pair 2 (Channels A2 & B2)(address 09h) Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch) Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh) ..................................................................... 37 6.6.1 Channel A Volume = Channel B Volume (A=B) .................................................................... 37 6.6.2 ATAPI Channel Mixing and Muting (ATAPI) .......................................................................... 37 6.6.3 Functional Mode (FM) ........................................................................................................... 38 6.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) ........................................................ 39 6.7.1 Mute (MUTE) ......................................................................................................................... 39 6.7.2 Volume Control (xx_VOL) ..................................................................................................... 39 6.8 Chip Revision (address 12h) ......................................................................................................... 40 6.8.1 Part Number ID (part) [Read Only] ........................................................................................ 40 7. FILTER PLOTS ..................................................................................................................................... 41 8. PARAMETER DEFINITIONS ................................................................................................................ 45 9. PACKAGE DIMENSIONS .................................................................................................................... 46 10. ORDERING INFORMATION .............................................................................................................. 47 11. REFERENCES .................................................................................................................................... 47 12. REVISION HISTORY ......................................................................................................................... 47
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CS4382A
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing..................................................................................................... Figure 2. Direct Stream Digital - Serial Audio Input Timing....................................................................... Figure 3. Control Port Timing - IC Format................................................................................................ Figure 4. Control Port Timing - SPI Format............................................................................................... Figure 5. Typical Connection Diagram, Software Mode............................................................................ Figure 6. Typical Connection Diagram, Hardware Mode .......................................................................... Figure 7. Format 0 - Left-Justified up to 24-bit Data ................................................................................. Figure 8. Format 1 - IS up to 24-bit Data ................................................................................................. Figure 9. Format 2 - Right-Justified 16-bit Data ........................................................................................ Figure 10. Format 3 - Right-Justified 24-bit Data ...................................................................................... Figure 11. Format 4 - Right-Justified 20-bit Data ...................................................................................... Figure 12. Format 5 - Right-Justified 18-bit Data ...................................................................................... Figure 13. De-Emphasis Curve................................................................................................................. Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) .............................................................. Figure 15. Full-Scale Output ..................................................................................................................... Figure 16. Recommended Output Filter.................................................................................................... Figure 17. Control Port Timing, IC Mode ................................................................................................. Figure 18. Control Port Timing, SPI Mode ................................................................................................ Figure 19. Single-Speed (fast) Stopband Rejection.................................................................................. Figure 20. Single-Speed (fast) Transition Band ........................................................................................ Figure 21. Single-Speed (fast) Transition Band (detail) ............................................................................ Figure 22. Single-Speed (fast) Passband Ripple ...................................................................................... Figure 23. Single-Speed (slow) Stopband Rejection ................................................................................ Figure 24. Single-Speed (slow) Transition Band....................................................................................... Figure 25. Single-Speed (slow) Transition Band (detail)........................................................................... Figure 26. Single-Speed (slow) Passband Ripple..................................................................................... Figure 27. Double-Speed (fast) Stopband Rejection ................................................................................ Figure 28. Double-Speed (fast) Transition Band....................................................................................... Figure 29. Double-Speed (fast) Transition Band (detail)........................................................................... Figure 30. Double-Speed (fast) Passband Ripple..................................................................................... Figure 31. Double-Speed (slow) Stopband Rejection ............................................................................... Figure 32. Double-Speed (slow) Transition Band ..................................................................................... Figure 33. Double-Speed (slow) Transition Band (detail) ......................................................................... Figure 34. Double-Speed (slow) Passband Ripple ................................................................................... Figure 35. Quad-Speed (fast) Stopband Rejection ................................................................................... Figure 36. Quad-Speed (fast) Transition Band ......................................................................................... Figure 37. Quad-Speed (fast) Transition Band (detail) ............................................................................. Figure 38. Quad-Speed (fast) Passband Ripple ....................................................................................... Figure 39. Quad-Speed (slow) Stopband Rejection.................................................................................. Figure 40. Quad-Speed (slow) Transition Band........................................................................................ Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................ Figure 42. Quad-Speed (slow) Passband Ripple...................................................................................... 14 15 16 17 18 19 22 22 22 22 23 23 24 24 26 26 29 29 41 41 41 41 41 41 42 42 42 42 42 42 43 43 43 43 43 43 44 44 44 44 44 44
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CS4382A
LIST OF TABLES
Table 1. Common Clock Frequencies........................................................................................................ 20 Table 2. Digital Interface Format, Stand-Alone Mode Options................................................................... 21 Table 3. Mode Selection, Stand-Alone Mode Options ............................................................................... 21 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................................ 21 Table 5. Digital Interface Formats - PCM Mode......................................................................................... 33 Table 6. Digital Interface Formats - DSD Mode ......................................................................................... 33 Table 7. ATAPI Decode ............................................................................................................................. 38 Table 8. Example Digital Volume Settings ................................................................................................. 39
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CS4382A 1. PIN DESCRIPTION
M3(DSD_SCLK) AOUTA1+ AOUTB1+ AOUTA1MUTEC1 AOUTB1-
DSDA3
DSDB3
48 47 46 45 44 43 42 41 40 39 38 37 DSDA2 DSDB1 DSDA1 VD GND MCLK LRCK(DSD_EN) SDIN1 SCLK TST SDIN2 TST 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 AOUTA2AOUTA2+ AOUTB2+ AOUTB2VA GND AOUTA3AOUTA3+ AOUTB3+ AOUTB3AOUTA4AOUTA4+
DSDB2
DSDA4
DSDB4 VLS
CS4382A
31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24 SDIN3 M2(SCL/CCLK) M1(SDA/CDIN) M0(AD0/CS) FILT+ AOUTB4+ VLC SDIN4 RST MUTEC2 VQ AOUTB4-
Pin Name
VD GND MCLK LRCK SDIN1 SDIN2 SDIN3 SDIN4 SCLK VLC RST FILT+
#
4 5 31 6 7 8 11 13 14 9 18 19 20
Pin Description
Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Should be connected to analog ground. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Serial Clock (Input) - Serial clock for the serial audio interface. Control Port Power (Input) - Determines the required signal level for the Control Port. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and the DC current is less than the maximum specified in the Analog Characteristics and Specifications section. Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
VQ
21
MUTEC1 MUTEC234
41 22
6
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CS4382A
Pin Name
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,VA VLS TST
#
Pin Description
39, 40 38, 37 35, 36 34, 33 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the 29, 30 Analog Characteristics specification table. 28, 27 25, 26 24, 23 32 43 10 12 Analog Power (Input) - Positive power supply for the analog section. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Test - These pins need to be tied to analog ground.
Software Mode Definitions SCL/CCLK SDA/CDIN AD0/CS 15 16 17 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. Requires an external pullup resistor to the logic interface voltage in IC Mode as shown in the Typical Connection Diagram. Serial Control Data (Input/Output) - SDA is a data I/O line in IC Mode and requires an external pullup resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input data line for the Control Port interface in SPI Mode. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip select signal for SPI format.
Stand-Alone Definitions M0 M1 M2 M3 DSD Definitions DSD_SCLK DSD_EN DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 42 7 3 2 1 48 47 46 45 44 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. DSD-Enable (Input) - When held at logic `1' the device will enter DSD Mode (Stand-Alone mode only). 17 16 15 42 Mode Selection (Input) - Determines the operational mode of the device.
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
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CS4382A 2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and TA = 25C.
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.) Parameters
DC Power Supply Analog power Digital internal power Serial data port interface power Control Port interface power -CQZ -DQZ
Symbol
VA VD VLS VLC TA
Min
4.75 2.37 1.71 1.71 -10 -40
Typ
5.0 2.5 5.0 5.0 -
Max
5.25 2.63 5.25 5.25 +70 +85
Units
V V V V
Specified Temperature Range
C C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.) Parameters
Analog power Digital internal power Serial data port interface power Control Port interface power Input Current Any Pin Except Supplies Digital Input Voltage Serial data port interface Control Port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply
Symbol
VA VD VLS VLC Iin VIND-S VIND-C Top Tstg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max
6.0 3.2 6.0 6.0 10 VLS+ 0.4 VLC+ 0.4 125 150
Units
V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
8
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CS4382A DAC ANALOG CHARACTERISTICS
Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 100 pF; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Parameters
Specified Temperature Range Dynamic Range A-weighted unweighted 16-bit A-weighted (Note 2) unweighted 24-bit 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB 24-bit
Symbol
TA
Min
-10 108 105 -
Typ
114 111 97 94 -100 -91 -51 -94 -74 -34 114 114 111 97 94 -100 -91 -51 -94 -74 -34 114
Max
70 -94 -45 85 -91 -42 -
Unit
C dB dB dB dB dB dB dB dB dB dB dB C dB dB dB dB dB dB dB dB dB dB dB
CS4382A-CQZ Dynamic Performance - All PCM Modes and DSD
Total Harmonic Distortion + Noise
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise ratio
CS4382A-DQZ Dynamic Performance - All PCM Modes and DSD
Specified Temperature Range Dynamic Range (Note 1) A-weighted unweighted 16-bit A-weighted (Note 2) unweighted 24-bit (Note 1) 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB 24-bit TA -40 105 102 -
Total Harmonic Distortion + Noise
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise ratio
Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Performance limited by 16-bit quantization noise.
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CS4382A DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)
Parameters
Interchannel Isolation (1 kHz)
Symbol
Min
132%*VA 94%*VA -
Typ
110 0.1 100 134%*VA 96%*VA 130 1.0 3 100 50% VA 10
Max
136%*VA 98%*VA -
Units
dB dB ppm/C Vpp Vpp mA k pF VDC A
DC Accuracy
Interchannel Gain Mismatch Gain Drift
Analog Output
Full Scale DifferentialPCM, DSD processor VFS Output Voltage Direct DSD Mode Output Impedance (Note 3) ZOUT Max DC Current draw from an AOUT pin IOUTmax Min AC-Load Resistance RL Max Load Capacitance CL Quiescent Voltage VQ IQMAX Max Current draw from VQ
POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies
Power Supply Current (Note 4) normal operation, VA= 5 V VD= 2.5 V (Note 5) Interface current, VLC=5 V VLS=5 V (Note 6) power-down state (all supplies) Power Dissipation (Note 4) VA = 5 V, VD = 2.5 V normal operation (Note 6) power-down Package Thermal Resistance (1 kHz) (60 Hz) IA ID ILC ILS Ipd 75 20 2 84 200 426 1 48 15 60 40 83 26 482 mA mA A A A mW mW C/Watt C/Watt dB dB
Symbol
Min
Typ
Max
Units
JA JC PSRR
Power Supply Rejection Ratio (Note 7)
Notes: 3. VFS is tested under load RL and includes attenuation due to ZOUT 4. Current consumption increases with increasing FS within a given speed mode and is signal-dependent. Max values are based on highest FS and highest MCLK. 5. ILC measured with no external loading on the SDA pin. 6. Power-Down Mode is defined as RST pin = Low with all clock and data lines held static. 7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
10
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CS4382A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See Note 12. Fast Roll-Off Parameter Min Typ Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) 0 0 -0.01 0.547 102 0 0 -0.01 .583 80 0 0 -0.01 .635 90 10.4/Fs 6.15/Fs 7.1/Fs
Max
.454 .499 +0.01 0.23 0.14 0.09 .430 .499 +0.01 .105 .490 +0.01 -
Unit
Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10)
Notes: 8. Slow roll-off interpolation filter is only available in Software Mode. 9. Response is clock-dependent and will scale with Fs. 10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hardware Mode. 12. Amplitude vs. Frequency plots of this data are available in Section 7. "Filter Plots" on page 41 .
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CS4382A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINED) Parameter Single-Speed Mode - 48 kHz
Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10)
Slow Roll-Off (Note 8) Min Typ Max
0 0 -0.01 .583 64 0 0 -0.01 .792 70 0 0 -0.01 .868 75 7.8/Fs 5.4/Fs 6.6/Fs 0.417 0.499 +0.01 0.36 0.21 0.14 .296 .499 +0.01 .104 .481 +0.01 -
Unit
Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
Double-Speed Mode - 96 kHz
Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay
Quad-Speed Mode - 192 kHz
Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz (Note 10)
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter DSD Processor mode
Passband (Note 9) Frequency Response Roll-off to -3 dB corner 10 Hz to 20 kHz 0 -0.05 27 50 +0.05 kHz dB dB/Oct
Min
Typ
Max
Unit
12
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CS4382A DIGITAL CHARACTERISTICS
Parameters
Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -1.2 mA) Low-Level Output Voltage (IOL = 1.2 mA) Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage (Note 13) Serial I/O Control I/O Serial I/O Control I/O Control I/O Control I/O
Symbol
Iin VIH VIH VIL VIL VOH VOL Imax VOH VOL
Min
70% 70% 80% -
Typ
8 3 VA 0
Max
10 30% 30% 20% -
Units
A pF VLS VLC VLS VLC VLC VLC mA V V
13. Any pin except supplies. Transient currents of up to 100 mA on the input pins will not cause SCR latchup
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CS4382A SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters
RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate - LRCK (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs (Note 14)
Symbol
Min
1 1.024 45 4 50 100 45 45
Max
55.2 55 54 108 216 55 55 -
Units
ms MHz % kHz kHz kHz % % ns ns ns ns ns
LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK Low Time LRCK Edge to SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge tsckh tsckl tlcks tds tdh
8 8 5 3 5
Notes: 14. After powering up, RST should be held low until after the power supplies and clocks are settled. 15. See Table 1 on page 20 for suggested MCLK frequencies.
LRCK
tlcks
tsckh
tsckl
SCLK
tds
SDINx
tdh
MSB MSB-1
Figure 1. Serial Audio Interface Timing
14
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CS4382A SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VLS; CL = 20 pF) Parameter
MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency
Symbol
tsclkl tsclkh
Min
40 160 160 1.024 2.048 20 20
Typ
-
Max
60 3.2 6.4 -
Unit
% ns ns MHz MHz ns ns
(64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time
tsdlrs tsdh
t sclkh t sclkl DSD_SCLK t sdlrs
DSDxx
t sdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
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CS4382A SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 16)
Symbol
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 1000
Unit
kHz ns s s s s s s ns s ns s ns
Notes: 16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 3. Control Port Timing - IC Format
16
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CS4382A SWITCHING CHARACTERISTICS - CONTROL PORT - SPITM FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter
CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 18) (Note 19) (Note 19) (Note 17)
Symbol
fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2
Min
500 500 1.0 20 66 66 40 15 -
Max
6 100 100
Unit
MHz ns ns s ns ns ns ns ns ns ns
Notes: 17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 18. Data must be held for sufficient time to bridge the transition time of CCLK. 19. For FSCK < 1 MHz.
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 4. Control Port Timing - SPI Format
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CS4382A 3. TYPICAL CONNECTION DIAGRAM
+2.5 V 1 F + 0.1 F 4 VD 32 VA AOUTA1+ AOUTA1AOUTB1+ 6 7 PCM Digital Audio Source 9 8 11 13 14
470
+5 V 0.1 F + 1 F
39 40 38 37 35 36 34 33 29 30 28 27 25 26 24 23
Analog Conditioning and Muting
220
MCLK LRCK SCLK SDIN1 SDIN2 SDIN3 SDIN4
AOUTB1AOUTA2+ AOUTA2AOUTB2+ AOUTB2AOUTA3+
Analog Conditioning and Muting
Analog Conditioning and Muting
Analog Conditioning and Muting
+1.8 V to +5 V
43 0.1 F
470
VLS
AOUTA3-
Analog Conditioning and Muting
CS4382A
AOUTB3+ AOUTB3-
Analog Conditioning and Muting
3 2 1
DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 DSD_SCLK AOUTA4+ AOUTA4AOUTB4+ AOUTB4-
Analog Conditioning and Muting
DSD Audio Source
48 47 46 45 44 42
Analog Conditioning and Muting
41 MUTEC1 MUTEC234 22
Mute Drive
19 MicroController 15 16 17 2 K 2 K
RST SCL/CCLK SDA/CDIN ADO/CS
Note* 18 0.1 F
FILT+ 20 VLC VQ 21 0.1 F + 1 F 0.1 F + 47 F
+1.8 V to +5 V
Note: Necessary for I C control port operation
2
GND 5
GND TST* 31 NOTETST: Pins 10 and 12
Figure 5. Typical Connection Diagram, Software Mode
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CS4382A
+2.5 V 1 F + 0.1 F 4 VD NoteDSD 47 K 32 VA AOUTA1+ AOUTA1AOUTB1+ 6 7 PCM Digital Audio Source 9 8 11 13 14
470
+5 V 0.1 F + 1 F
39 40 38 37 Analog Conditioning and Muting
VLS
220
MCLK LRCK SCLK SDIN1 SDIN2 SDIN3 SDIN4
AOUTB1-
Analog Conditioning and Muting
MUTEC1
41
Mute Drive
AOUTA2+ AOUTA2AOUTB2+
35 36 34 33 29 30 28 27 25 26 24 23 Analog Conditioning and Muting Analog Conditioning and Muting Analog Conditioning and Muting
+1.8 V to +5 V
43 0.1 F
VLS
CS4382A
AOUTB2AOUTA3+
Analog Conditioning and Muting
470
3 2 1
AOUTA3DSDA1 DSDB1 DSDA2 DSDB2 DSDA3 DSDB3 DSDA4 DSDB4 AOUTA4+ AOUTA4AOUTB4+ AOUTB4AOUTB3+ AOUTB3-
Analog Conditioning and Muting
DSD Audio Source
48 47 46 45 44 NoteDSD Optional 47 K
Analog Conditioning and Muting
42 15
M3(DSD_SCLK) M2 M1 M0 RST
MUTEC234
22
Mute Drive
Stand-Alone Mode Configuration
16 17 19
FILT+ 20 VQ +1.8 V to +5 V 18 0.1 F VLC 21 0.1 F + 1 F 0.1 F + 47 F
GND 5
GND 31
TST 10, 12 NoteDSD: For DSD operation: 1) LRCK must be tied to VLS and remain static high. 2) M3 PCM stand-alone configuration pin becomes DSD_SCLK
Figure 6. Typical Connection Diagram, Hardware Mode
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CS4382A 4. APPLICATIONS
The CS4382A serially accepts twos complement formatted PCM data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4382A can be configured in Hardware Mode by the M0, M1, M2 , M3 and DSD_EN pins and in Software Mode through IC or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.
Speed Mode (sample-rate range) MCLK Ratio Single-Speed (4 to 50 kHz) MCLK Ratio Double-Speed (50 to 100 kHz)
Sample Rate (kHz) 32 44.1 48 64 88.2 96 256x 8.1920 11.2896 12.2880 128x 8.1920 11.2896 12.2880 64x 11.2896 12.2880
MCLK (MHz) 384x 12.2880 16.9344 18.4320 192x 12.2880 16.9344 18.4320 96x 16.9344 18.4320 512x 16.3840 22.5792 24.5760 256x 16.3840 22.5792 24.5760 128x 22.5792 24.5760 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 192x 33.8688 36.8640
Software Mode Only 1024x* 32.7680 45.1584 49.1520 512x* 32.7680 45.1584 49.1520 256x* 45.1584 49.1520
MCLK Ratio 176.4 Quad-Speed (100 to 200 kHz) 192 Note:
These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
4.2
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The state of these pins are continually scanned for any changes. These pins require connection to supply or ground as outlined in Figure 6. For M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these pins. In Software Mode, the operational mode and data format are set in the FM and DIF registers. See "Filter Plots" on page 41.
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M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data
Table 2. Digital Interface Format, Stand-Alone Mode Options
FORMAT 0 1 2 3
FIGURE Figure 7 Figure 8 Figure 9 Figure 10
M3 0 0 1 1
M2 (DEM) 0 1 0 1
DESCRIPTION Single-Speed without De-Emphasis (4 to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 13 Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates)
Table 3. Mode Selection, Stand-Alone Mode Options
DSD_EN (LRCK) 1 1 1 1 1 1 1 1
M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options
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CS4382A
4.3 Digital Interface Formats
The serial port operates as a slave and supports the IS, Left-Justified, and Right-Justified digital interface formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the rising edge.
LRCK SCLK
Left Channel
Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 7. Format 0 - Left-Justified up to 24-bit Data
LRCK SCLK
Left Channel
Right Channel
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 8. Format 1 - IS up to 24-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 9. Format 2 - Right-Justified 16-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Figure 10. Format 3 - Right-Justified 24-bit Data
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LRCK
Left Channel
Right Channel
SCLK
SDINx
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 11. Format 4 - Right-Justified 20-bit Data
LRCK
Left Channel
Right Channel
SCLK
SDINx
10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 12. Format 5 - Right-Justified 18-bit Data
4.4
Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the DSD_EN, M3 and M2 pins in Hardware Mode or the FM bits in Software Mode. SingleSpeed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorporates selectable interpolation filters for each mode of operation. A "fast" and a "slow" roll-off filter is available in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the "Filter Plots" on page 41 for more details). When in Hardware Mode, only the "fast" roll-off filter is available. Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to 42.
4.6
De-Emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been selected.
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CS4382A
In Software Mode, the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected via the de-emphasis control bits. In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected, the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual Fs over 44,100.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 13. De-Emphasis Curve
4.7
ATAPI Specification
The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 8 on page 39 and Figure 14 for additional information.
Left Channel Audio Data
A Channel Volume Control
MUTE
Aout Ax
SDINx
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutBx
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
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CS4382A
4.8 Direct Stream Digital (DSD) Mode
In Stand-Alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio. In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio. During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except LRCK in Stand-Alone Mode). When the DSD related pins are not being used, they should either be tied static low or remain active with clocks (except M3 in Stand-Alone Mode).
4.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4382A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4382A should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements.
4.10
Analog Output and Filtering
The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4382A evaluation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale output level to below 2 Vrms. Figure 15 shows how the full-scale differential analog output level specification is derived.
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CS4382A
AOUT+
4.175 V 2.5 V 0.825 V
4.175 V AOUT2.5 V 0.825 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 15. Full-Scale Output
Figure 16. Recommended Output Filter
4.11
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended, single-supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4382A data sheet for a suggested mute circuit.
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4.12 Recommended Power-Up Sequence
4.12.1 Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. If RST can not be held low long enough the SDINx pins should remain static low until all other clocks are stable, and if possible the RST should be toggled low again once the system is stable. 2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.12.2 Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings; FILT+ will remain low, and VQ will be connected to VA/2. 2. Bring RST high. The device will remain in a low-power state with FILT+ low for 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode). 3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the format and mode control bits to the desired settings. If more than the stated number of LRCK cycles passes before CPEN bit is written, the chip will enter Hardware Mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be set in time, the SDINx pins should remain static low (this way, no audio data can be converted incorrectly by the Hardware Mode settings). 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 s.
4.13
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources). The mute bits may then be released after clocks have settled and the proper modes have been set. It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met during clock source changes.
4.14
Control Port Interface
The Control Port is used to load all the internal register settings in order to operate in Software Mode (see the "Filter Plots" on page 41). The operation of the Control Port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. The Control Port operates in one of two modes: IC or SPI.
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CS4382A
4.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
4.14.2 IC Mode
In the IC Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial Control Port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as required, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected.
4.14.2.1 IC Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifications in Section 2. 1. Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This byte points to the register to be written. 3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by the MAP. 4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
4.14.2.2 IC Read
To read from the device, follow the procedure below while adhering to the Control Port Switching Specifications. 1. Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see Section 4.14.1) if an IC read is the first operation performed on the device. 3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read; then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the IC Write
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instructions followed by step 1 of the IC Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus.
N ote 1 SDA
001100 ADDR AD 0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL Start Stop
N ote: If operation is a w rite, th is byte contain s the M em o ry A ddress P ointer, M A P.
Figure 17. Control Port Timing, IC Mode
4.14.3 SPITM Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK (see Figure 18 for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifications in Section 2. 1. Bring CS low. 2. The address byte on the CDIN pin must then be 00110000. 3. Write to the memory address pointer, MAP. This byte points to the register to be written. 4. Write the desired data to the register pointed to by the MAP. 5. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.
CS CCLK CHIP ADDRESS C DIN
0011000
R/W
MAP
MSB
DATA
LSB
byte 1 M AP = M em ory Address Pointer
byte n
Figure 18. Control Port Timing, SPI Mode
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CS4382A
4.15 Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
4.16
INCR (Auto Map Increment Enable)
Default = `0' 0 - Disabled 1 - Enabled
4.16.1 MAP4-0 (Memory Address Pointer)
Default = `00000'
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CS4382A 5. REGISTER QUICK REFERENCE
Addr
01h 02h 03h 04h 05h 06h
Function
Mode Control 1 default Mode Control 2 default Mode Control 3 default Filter Control default Invert Control default Mixing Control Pair 1 (AOUTx1) default Vol. Control A1 default Vol. Control B1 default Mixing Control Pair 2 (AOUTx2) default Vol. Control A2 default Vol. Control B2 default Mixing Control Pair 3 (AOUTx3) default Vol. Control A3 default Vol. Control B3 default Mixing Control Pair 4 (AOUTx4) default Vol. Control A4 default Vol. Control B4 default Chip Revision default
7
CPEN 0 Reserved 0 SZC1 1 Reserved 0 INV_B4 0 P1_A=B 0 A1_MUTE 0 B1_MUTE 0 P2_A=B 0 A2_MUTE 0 B2_MUTE 0 P3_A=B 0 A3_MUTE 0 B3_MUTE 0 P4_A=B 0 A4_MUTE 0 B4_MUTE 0 PART4 0
6
5
4
3
2
1
0
PDN 1 Reserved 0 MUTEC 0 RMP_DN 0 INV_A1 0 FM0 0 A1_VOL0 0 B1_VOL0 0 Reserved 0 A2_VOL0 0 B2_VOL0 0 Reserved 0 A3_VOL0 0 B3_VOL0 0 Reserved 0 A4_VOL0 0 B4_VOL0 0 REV x
FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS 0 0 0 0 0 0 DIF2 DIF1 DIF0 Reserved Reserved Reserved 0 0 0 0 0 0 SZC0 SNGLVOL RMP_UP MUTEC+/AMUTE Reserved 0 0 0 0 1 0 Reserved Reserved FILT_SEL Reserved DEM1 DEM0 0 0 0 0 0 0 INV_B3 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 0 0 0 0 0 0 P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 FM1 0 A1_VOL6 0 B1_VOL6 0 P2ATAPI4 0 A2_VOL6 0 B2_VOL6 0 P3ATAPI4 0 A3_VOL6 0 B3_VOL6 0 P4ATAPI4 0 A4_VOL6 0 B4_VOL6 0 PART3 1 1 A1_VOL5 0 B1_VOL5 0 P2ATAPI3 1 A2_VOL5 0 B2_VOL5 0 P3ATAPI3 1 A3_VOL5 0 B3_VOL5 0 P4ATAPI4 1 A4_VOL5 0 B4_VOL5 0 PART2 1 0 A1_VOL4 0 B1_VOL4 0 P2ATAPI2 0 A2_VOL4 0 B2_VOL4 0 P3ATAPI2 0 A3_VOL4 0 B3_VOL4 0 P4ATAPI2 0 A4_VOL4 0 B4_VOL4 0 PART1 1 0 A1_VOL3 0 B1_VOL3 0 P2ATAPI1 0 A2_VOL3 0 B2_VOL3 0 P3ATAPI1 0 A3_VOL3 0 B3_VOL3 0 P4ATAPI1 0 A4_VOL3 0 B4_VOL3 0 PART0 0 1 A1_VOL2 0 B1_VOL2 0 P2ATAPI0 1 A2_VOL2 0 B2_VOL2 0 P3ATAPI0 1 A3_VOL2 0 B3_VOL2 0 P4ATAPI0 1 A4_VOL2 0 B4_VOL2 0 REV x 0 A1_VOL1 0 B1_VOL1 0 Reserved 0 A2_VOL1 0 B2_VOL1 0 Reserved 0 A3_VOL1 0 B3_VOL1 0 Reserved 0 A4_VOL1 0 B4_VOL1 0 REV x
07h 08h 09h
0Ah 0Bh 0Ch
0Dh 0Eh 0Fh
10h 11h 12h
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CS4382A 6. REGISTER DESCRIPTION
Note: All registers are read/write in IC Mode and write only in SPI, unless otherwise noted.
6.1
Mode Control 1 (address 01h)
7 CPEN 0 6 FREEZE 0 5 MCLKDIV 0 4 DAC4_DIS 0 3 DAC3_DIS 0 2 DAC2_DIS 0 1 DAC1_DIS 0 0 PDN 1
6.1.1
Control Port Enable (CPEN)
Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should write this bit within 10 ms following the release of Reset.
6.1.2
Freeze Controls (Freeze)
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
6.1.3
Master Clock DIVIDE ENABLE (mclkdiv)
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.
6.1.4
DAC Pair Disable (DACx_DIS)
Default = 0 0 - Enabled 1 - Disabled Function: When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility of audible artifacts.
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6.1.5 Power Down (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation in Control Port Mode can occur.
6.2
Mode Control 2 (address 02h)
6 DIF2 0 5 DIF1 0 4 DIF0 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
7 Reserved 0
6.2.1
Digital Interface Format (dif)
Default = 000 - Format 0 (Left-Justified, up to 24-bit data) Function: These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD Mode is selected. PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 7-12. DIF1 DIF0 DESCRIPTION Format FIGURE
0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data Reserved Reserved Table 5. Digital Interface Formats - PCM Mode 0 1 2 3 4 5 7 8 9 10 11 12
DIF2
0 0 0 0 1 1 1 1
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required master clock-to-DSD-data-rate is defined by the Digital Interface Format pins. DIF2 DIF1 DIFO DESCRIPTION
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
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33
CS4382A
6.2.2
7 SZC1 1
Mode Control 3 (address 03h)
6 SZC0 0 5 SNGLVOL 0 4 RMP_UP 0 3 MUTEC+/0 2 AMUTE 1 1 Reserved 0 0 MUTEC 0
6.2.3
Soft Ramp and Zero Cross CONTROL (SZC)
Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
6.2.4
Single Volume Control (Snglvol)
Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
34
DS618PP2
CS4382A
6.2.5 Soft Volume Ramp-Up after Error (RMP_UP)
Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in these instances. Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
6.2.6
MUTEC Polarity (MUTEC+/-)
Default = 0 0 - Active High 1 - Active Low Function: The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Notes:
When the onboard mute circuitry is designed for active low, the MUTEC outputs will be high (un-muted) for the period of time during reset and before this bit is enabled to 1.
6.2.7
Auto-Mute (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
6.3
Mutec Pin Control (MUTEC)
Default = 0 0 - Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to `0', a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to `1', a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 5.
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CS4382A
6.4 Filter Control (address 04h)
6 Reserved 0 5 Reserved 0 4 FILT_SEL 0 3 Reserved 0 2 DEM1 0 1 DEM0 0 0 RMP_DN 0 7 Reserved 0
6.4.1
Interpolation Filter Select (FILT_SEL)
Default = 0 0 - Fast roll-off 1 - Slow roll-off Function: This function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter characteristics, please see Section 2.
6.4.2
De-Emphasis Control (DEM)
Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 13) De-emphasis is only available in Single-Speed Mode.
6.4.3
Soft Ramp-Down before Filter Mode Change (RMP_DN)
Default = 0 0 - Disabled 1 - Enabled Function: If either the FILT_SEL or DEM bits are changed, the DAC will stop conversion for a period of time to change filter values. This bit selects how the data is effected prior to and after the change of the filter values. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp from mute to the original volume value after a filter-mode change according to the settings of the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is performed. Loss of clocks or a change in the FM bits will always cause an immediate mute; unmute in these conditions is affected by the RMP_UP bit.
Notes:
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
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DS618PP2
CS4382A
6.5 Invert Control (address 05h)
6 INV_A4 0 5 INV_B3 0 4 INV_A3 0 3 INV_B2 0 2 INV_A2 0 1 INV_B1 0 0 INV_A1 0 7 INV_B4 0
6.5.1
Invert Signal Polarity (Inv_Xx)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
6.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h) Mixing Control Pair 2 (Channels A2 & B2)(address 09h) Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch) Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)
6 PxATAPI4 0 5 PxATAPI3 1 4 PxATAPI2 0 3 PxATAPI1 0 2 PxATAPI0 1 1 PxFM1 0 0 PxFM0 0
7 Px_A=B 0
6.6.1
Channel A Volume = Channel B Volume (A=B)
Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
6.6.2
ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
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CS4382A
ATAPI4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ATAPI3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ATAPI2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ATAPI1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ATAPI0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AOUTAx
MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2]
AOUTBx
MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
Table 7. ATAPI Decode
6.6.3
Functional Mode (FM)
Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the same functional mode setting before a speed-mode change is accepted. When DSD Mode is selected for any channel pair, all pairs switch to DSD Mode.
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DS618PP2
CS4382A
6.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
6 xx_VOL6 0 5 xx_VOL5 0 4 xx_VOL4 0 3 xx_VOL3 0 2 xx_VOL2 0 1 xx_VOL1 0 0 xx_VOL0 0 7 xx_MUTE 0
Note:
These eight registers provide individual volume and mute control for each of the eight channels. The values for "xx" in the bit fields above are as follows: Register address 07h - xx = A1 Register address 08h - xx = B1 Register address 0Ah - xx = A2 Register address 0Bh - xx = B2 Register address 0Dh - xx = A3 Register address 0Eh - xx = B3 Register address 10h - xx = A4 Register address 11h - xx = B4
6.7.1
Mute (MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bit.
6.7.2
Volume Control (xx_VOL)
Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling the MUTE bit. Binary Code
0000000 0010100 0101000 0111100 1011010
Decimal Value
0 20 40 60 90
Volume Setting
0 dB -20 dB -40 dB -60 dB -90 dB
Table 8. Example Digital Volume Settings
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CS4382A
6.8 Chip Revision (address 12h)
7 PART4 0 6 PART3 1 5 PART2 1 4 PART1 1 3 PART0 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
6.8.1
Part Number ID (part) [Read Only]
01110 - CS4382A 000 - Revision A Function: This read-only register can be used to identify the model and revision number of the device.
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DS618PP2
CS4382A 7. FILTER PLOTS
0 0
-20
-20
Amplitude (dB)
Amplitude (dB)
-40
-40
-60
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 19. Single-Speed (fast) Stopband Rejection
0
Figure 20. Single-Speed (fast) Transition Band
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 21. Single-Speed (fast) Transition Band (detail)
Figure 22. Single-Speed (fast) Passband Ripple
0
0
-20
-20
Amplitude (dB)
-60
Amplitude (dB)
-40
-40
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 23. Single-Speed (slow) Stopband Rejection
Figure 24. Single-Speed (slow) Transition Band
DS618PP2
41
CS4382A
0 0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 25. Single-Speed (slow) Transition Band (detail)
Figure 26. Single-Speed (slow) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 27. Double-Speed (fast) Stopband Rejection
0
Figure 28. Double-Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 29. Double-Speed (fast) Transition Band (detail)
Figure 30. Double-Speed (fast) Passband Ripple
42
DS618PP2
CS4382A
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 31. Double-Speed (slow) Stopband Rejection
0
Figure 32. Double-Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 33. Double-Speed (slow) Transition Band (detail)
Figure 34. Double-Speed (slow) Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 35. Quad-Speed (fast) Stopband Rejection
Figure 36. Quad-Speed (fast) Transition Band
DS618PP2
43
CS4382A
0.2
0
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 37. Quad-Speed (fast) Transition Band (detail)
Figure 38. Quad-Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 39. Quad-Speed (slow) Stopband Rejection
0
Figure 40. Quad-Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 41. Quad-Speed (slow) Transition Band (detail)
Figure 42. Quad-Speed (slow) Passband Ripple
44
DS618PP2
CS4382A 8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
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45
CS4382A 9. PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES NOM
0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4
DIM
A A1 B D D1 E E1 e* L
MIN
--0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000
MAX
0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
MIN
--0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00
MILLIMETERS NOM
1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4
MAX
1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00
* Nominal pin pitch is 0.50 mmControlling dimension is mm. JEDEC Designation: MS022
46
DS618PP2
CS4382A 10.ORDERING INFORMATION
Product CS4382A Description 114 dB, 192 kHz 8channel D/A Converter Package 48-pin LQFP Pb-Free YES Automotive -40 to +85 C Grade Commercial Temp Range -10 to +70 C Container Tray Tape & Reel Tray Tape & Reel Order # CS4382A-CQZ CS4382A-CQZR CS4382A-DQZ CS4382A-DQZR CDB4382A
CDB4382A CS4382A Evaluation Board
11.REFERENCES
1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4382A Datasheet 3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48 4. The IC-Bus Specification: Version 2.0, Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
12.REVISION HISTORY
Release
PP1
PP2
Changes Updated output impedance spec on page 10 Improved interchannel isolation spec on page 10 Updated legal text Reformatted ordering information Corrected package type
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
DS618PP2
47

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